The embodiments herein relate to integrated circuit (IC) design, and more specifically, to methods, systems, and computers that optimize the number of decoupling capacitors within integrated circuit designs.
In integrated circuits, decoupling capacitors help to stabilize the on-chip VDD to GND power supply. A common design objective involves satisfying a power-supply compression target, which is a quantitative measure of how much voltage stability the decoupling capacitors provide when the circuits on the chip are switching. Specifically, power-supply compression can be described as the difference between the nominal on-chip power supply voltage value (i.e., VDD−GND) before a switching event, and the minimum on-chip power supply voltage value that occurs during a switching event.
Very early in the process of integrated circuit design, one of the major challenges is to determine how many decoupling capacitors are required to meet the voltage compression specification. Another challenge involves properly allocating the decoupling capacitors to ensure that they are placed in optimal proximity to the switching circuits that induce power-supply voltage variation. Some early design strategies assume worst-case switching scenarios and yield correspondingly conservative estimates of required decoupling capacitance. These approaches may drive unnecessary costs due to the finite and non-negligible area consumed by the decoupling capacitors. Conversely, less conservative approaches may underpredict decoupling capacitor requirements, and actually compromise circuit function or performance. This can occur if the constraints imposed by early design decisions prohibit the inclusion of additional decoupling capacitors ultimately deemed necessary following more “detailed” voltage compression analysis. Thus, it is desirable to obtain accurate estimates of the decoupling capacitor requirements very early in the design cycle.
Accurate early decoupling capacitor estimation is a challenging design problem. Simple guidelines have frequently been utilized, but these are commonly derived solely from the charge-sharing relationships between the decoupling capacitance and the representative switching-event “switched” capacitance. This approach makes it difficult to account for the contribution of decoupling capacitor resistance to power-supply voltage compression. Moreover, practical IC designs contain multiple IP (intellectual property) circuit components, which may interactively switch in complex ways. These interactions are known to play a significant role in determining how many decoupling capacitors are required. Finally, the switched-capacitance equivalent of any switching circuit is a function of its operating frequency, and its corresponding charge demand is typically provided not only by assigned decoupling capacitors, but also by system-level charge reservoirs like package- and circuit-board capacitors, and even the board voltage regulation module. It is extremely difficult to quantify the effect of these charge transfer mechanisms using a guideline-based design approach.
Alternative techniques for decoupling capacitor allocation use circuit simulation, and vary widely in scope and complexity. Rigorous analysis using highly detailed simulation models can address all of the drawbacks inherent to “guideline-based” strategies, but suffer from their reliance on extracted power bus models and/or physical layout data. Lumped simulation models, which use engineering approximations to simplify their complexity, have also proven useful for decoupling capacitor estimation.
Lumped element analysis can intelligently combine the effects of parasitic circuit elements which comprise more elaborate power distribution models, but typically model the power demand of individual switching circuits collectively. As a result, any individual circuits deemed power-supply “aggressors” may not be uniquely modeled. While this approach provides a clear performance advantage and is useful for estimating the total decoupling capacitor requirement, the results of lumped-element results provide little guidance for assigning decoupling capacitors to the individual aggressors, whose details are “lost” in any modeling approximation. Any attempts to represent aggressors individually in a lumped-element model, again, create dependencies on circuit placement and layout which, practically speaking, are best avoided during early-stage design analysis. The approach described herein overcomes these limitations by providing clear guidance on decoupling capacitor assignment to individual circuits without utilizing or assuming any knowledge of circuit placement or layout.